Course AssignmentSystem LSI Design

教授的6个基础test pattern仿真测试

  • 首先，电脑中必须安装iverilog并配置用户的环境变量。
  • 将文件夹下的pcpu.v粘贴修改为自己写好的pcpu.v，然后直接运行run.bat即可在cmd终端查看测试结果。

测试结果如下，测试通过的项目会打上○，未通过则是×。本代码经过测试AC：

注意事项

  • 自己书写的pcpu模块，其管教的顺序必须和测试代码中的保持一致，如果不保持一致必然报错。我之前因为要添加新功能，因此在原有的pcpu模块中添加了一个管教，这导致了所有的测试样例全部不通过！我们打开测试代码，可以看到实例化pcpu的部分如下：
  • 其他注意事项写在代码注释中。

代码（基础版：能够通过教授所有的test pattern）

基础版，能够通过教授所有的test pattern。但是相对应的，为了满足测试要求，我关闭了特色功能LWC_INTERRUPT和LWC_CALLBACK：代码中本应该作为输入管教的 i_datain_interrupt 被替代为一个恒为0的reg变量，因此状态机也不会跳转到interrupt中，只会在最基础的idle和exe之间跳转，实现最基础的27条指令。

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`define NOP   5'b00000
`define HALT  5'b00001
`define LOAD  5'b00010
`define STORE 5'b00011
`define ADD   5'b01000
`define CMP   5'b01100
`define BZ    5'b11010
`define BN    5'b11100
//[------------- LUWEICHENG -------------]
// Basic operations
`define SUB   5'b01010
`define SUBC  5'b10010
`define ADDC  5'b10001
`define ADDI  5'b01001
`define SUBI  5'b01011
`define LDIH  5'b10000
// Logical/Shift operations
`define AND   5'b01101
`define OR    5'b01110
`define XOR   5'b01111
`define SLL   5'b00100
`define SRL   5'b00101
`define SLA   5'b00110
`define SRA   5'b00111
// Control operations
`define JUMP  5'b11000
`define JMPR  5'b11001
`define BNZ   5'b11011
`define BNN   5'b11101
`define BC    5'b11110
`define BNC   5'b11111 
//** LWC original operations
`define LWC_CLEAR       5'b10011   //clear: clear one data in rg[val3] 【CLEAR null null val3】
`define LWC_CA          5'b10100   //CA: celete all data in rg  【no op1op2op3, like NOP & HALT】
`define LWC_ENCRYPT     5'b10101   //encrypt: 数据加密  【LWC_ENCRYPT r1 r2 r3】  秘钥：r3; 源码：r2；加密结果存放在r1，秘钥存放在r1+1.
`define LWC_INTERRUPT   5'b10110   //Interrupt: 中断 (Control operation)  
`define LWC_CALLBACK    5'b10111   //CallBack: 中断回调
//[------------- LUWEICHENG -------------]

// FSM for CPU controler
`define idle 2'b00
`define exec 2'b01
`define interrupt 2'b10


module pcpu (reset, clock, enable, start, i_addr, i_datain, d_addr,
             d_datain, d_dataout, d_we, select_y, y);

input reset, enable, start, clock;   //由顶层于外部连接，由外部(仿真时)控制
input  [15:0] i_datain;
//input  [15:0] i_datain_interrupt;   //仅做基础test pattern测试时，需要关闭interrupt功能。
output [7:0]  i_addr;
output [7:0]  d_addr;
input  [15:0] d_datain;
output [15:0] d_dataout;
output d_we;

// for Debug ------------ 只是用y看一下内部各个线上的数据
input  [3:0] select_y;
output [15:0] y; 

//--2025.2.5:For Basic Tests--//
reg i_datain_interrupt;

// Definition of F/Fs
reg [7:0]  pc ;                              //pc:  取指令的指针，指向imem内下一条要执行的指令。
reg [15:0] id_ir, ex_ir, mem_ir, wb_ir;      //xx_ir: 指令链，不同阶段对指令instruction进行流水线式的存储。
reg [15:0] gr [0:7];                         //gr: General Register。它是CPU内部的存储器(寄存器堆)。
reg [15:0] reg_A, reg_B, reg_C, reg_C1;      //reg_X: 数据寄存器，用于CPU内部运算数据的暂存。 [reg_A,reg_B] --> ALU --> [reg_C]
reg [15:0] smdr, smdr1;                      //smdr: 直接存储数据
reg zf, nf, dw;       //flags:  zf(zero flag);  nf(negative flag);  dw(data write):与d_we相连，是CPU->dmem写使能。
//[------------- LUWEICHENG -------------]
reg cf;                  //carry flag: 进位信号
reg[7:0] pc_interrupt;   //记录中断前的pc值，中断回调后pc置为 pc_interrupt+1
reg inter_flag;
//[------------- LUWEICHENG -------------]
reg[1:0] state;

// Definition of temporary variables
reg [15:0] ALUo;
reg [15:0] y;
reg[1:0] next_state;

assign i_addr = pc;  //pc给到i_addr，i_addr输出到imem，取出一条指令
assign d_we  = dw;
assign d_addr = reg_C[7:0];   //从dmem中取data的地址，地址始终存在reg_C中
assign d_dataout = smdr1;


// CPU Control (FSM)
always @(posedge clock or negedge reset)
    begin
      if (!reset)
         state <= `idle;
      else
         state <= next_state;
    end

always @(state or enable or start or wb_ir[15:11])
    begin
       case (state)
        `idle : if ((enable == 1'b1) && (start == 1'b1))
                   next_state <= `exec;
                else
                   next_state <= `idle;
        `exec : if ((enable == 1'b0) || (wb_ir[15:11] == `HALT))
                   next_state <= `idle;
                else if ((enable == 1'b0) || (id_ir[15:11] == `LWC_INTERRUPT))
                   next_state <= `interrupt;
                else
                   next_state <= `exec;
        `interrupt: if (id_ir[15:11] == `LWC_CALLBACK)
                        next_state <= `exec;
                    else
                        next_state <= `interrupt;
      endcase
     end
 
// IF Block (1st Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         id_ir <= 16'b0000000000000000;
         pc    <= 8'b00000000;
         pc_interrupt <= 8'b00000000;
         inter_flag <= 0;
		 i_datain_interrupt <= 0;   //for professor's test pattern, close INTERRUPT using ‘i_datain_interrupt===0’
       end
     else if(state==`exec||state==`interrupt)
       begin
         // id_ir <= i_datain;     //从imem取指令
         id_ir <= (state == `interrupt) ? i_datain_interrupt : i_datain;
        //主要任务：pc指针控制
         if ( ((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1)) ||
              (mem_ir[15:11] == `JMPR) ||
              ((mem_ir[15:11] == `BNZ) && (zf == 1'b0)) || ((mem_ir[15:11] == `BNN) && (nf == 1'b0)) || ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0)) )      
            //特殊指令跳转： jump to reg_C[7:0]，跳转到ALU运算出来的指令地址。因此必须要根据mem阶段的指令mem_ir判断，否则还没有运算出跳转结果reg_C
            pc <= reg_C[7:0];  
         else if (id_ir[15:11] == `JUMP)    
            //JUMP指令跳转: jump to {val2,val3}, 中括号的意思是[7:4]与[3:0]组合为[7:0]
            pc <= id_ir[7:0];  
         //[------------- LUWEICHENG -------------]   
		 /*
         //LOAD需要等一拍： 等待运算完成，ALUo值存入rg后，再取值
         else if ((id_ir[15:11] == `LOAD) && (i_datain[15:11]!=`JUMP) && (i_datain[15:11]!=`NOP) && (i_datain[15:11]!=`HALT) && (i_datain[15:11]!=`LOAD))
         begin
            if ( (id_ir[10:8] == i_datain[2:0]) && 
                 ((i_datain[15:11]==`ADD) || (i_datain[15:11]==`ADDC) || (i_datain[15:11]==`SUB) || (i_datain[15:11]==`SUBC) || (i_datain[15:11]==`CMP) || 
                  (i_datain[15:11]==`AND) || (i_datain[15:11]==`OR) || (i_datain[15:11]==`XOR)) )
            begin   pc <= pc;   id_ir <= 16'bXXXXXXXXXXXXXXXX;  end
            else if ( (id_ir[10:8] == i_datain[6:4]) &&
                     ((i_datain[15:11]==`STORE)|| 
                     (i_datain[15:11]==`CMP)|| (i_datain[15:11]==`ADD) || (i_datain[15:11]==`ADDC) || (i_datain[15:11]==`SUB) || (i_datain[15:11]==`SUBC) ||
                     (i_datain[15:11]==`AND)|| (i_datain[15:11]==`OR) || (i_datain[15:11]==`XOR) ||
                     (i_datain[15:11]==`SLL)|| (i_datain[15:11]==`SRL) || (i_datain[15:11]==`SLA)|| (i_datain[15:11]==`SRA)) )
            begin   pc <= pc;   id_ir <= 16'bXXXXXXXXXXXXXXXX;  end
            else if ( (id_ir[10:8] == i_datain[10:8]) && 
                      ((i_datain[15:11]==`STORE) || 
                      (i_datain[15:11]==`LDIH) || (i_datain[15:11]==`SUBI) || 
                      (i_datain[15:11]==`JMPR) || (i_datain[15:11]==`BZ) || (i_datain[15:11]==`BNZ) || (i_datain[15:11]==`BN) || (i_datain[15:11]==`BNN) || (i_datain[15:11]==`BC) || (i_datain[15:11]==`BNC)))
            begin   pc <= pc;   id_ir <= 16'bXXXXXXXXXXXXXXXX;  end
            else    ;
         end
		 */
         //[------------- LUWEICHENG -------------]
         
         //[------------- LUWEICHENG -------------] 
         //interrupt & callback
         else if (id_ir[15:11] == `LWC_INTERRUPT)  begin
            pc <= 0;                                         //转到imem_interrupt,从0开始
            if(inter_flag == 0) begin
                pc_interrupt <= pc;                           //记录中断前的pc值
                inter_flag <= 1;
            end
         end
         else if (id_ir[15:11] == `LWC_CALLBACK)  begin
            pc <= pc_interrupt;                                //回到imem
         end
          //[------------- LUWEICHENG -------------]
         else
            pc <= pc + 1;
       end
     else if(state==`idle)   //pc停止
        pc <= pc;
     else ;
    end
 
// ID Block (2nd Stage)
always @(posedge clock or negedge reset)
begin
     if (!reset)
       begin
         ex_ir <= 16'b0000000000000000;
         reg_A <= 16'b0000000000000000;
         reg_B <= 16'b0000000000000000;
         smdr  <= 16'b0000000000000000;
       end
     else if(state==`exec||state==`interrupt)
     begin
         ex_ir <= id_ir;   //ir传递（id -> ex）
         //[------------- LUWEICHENG -------------]
         //The general register clearing operations LWC_CLEAR and LWC_CA are executed 
         //directly in the ID stage, no need to wait until the WB
         if (id_ir[15:11] == `LWC_CA)   begin
            gr[0] = 16'b0000000000000000;   
            gr[1] = 16'b0000000000000000;
            gr[2] = 16'b0000000000000000;
            gr[3] = 16'b0000000000000000;
            gr[4] = 16'b0000000000000000;
            gr[5] = 16'b0000000000000000;
            gr[6] = 16'b0000000000000000;
            gr[7] = 16'b0000000000000000;           
         end
         else if (id_ir[15:11] == `LWC_CLEAR) begin  //clear: clear one data in rg[val3] 【CLEAR null null val3】
            gr[id_ir[3:0]] = 16'b0000000000000000;
         end
         else   ;
         //[------------- LUWEICHENG -------------]
         /******************** 
            reg_A 赋予：第一个操作数  ***************************************************************************************************************
         *********************/
         //↓[type:I]  r1  val2  val3 形 
         if ((id_ir[15:11] == `ADDI) || (id_ir[15:11] == `SUBI) || (id_ir[15:11] == `LDIH) ||
             (id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) ||
             (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC)) 
           begin
           //[------------- LUWEICHENG -------------]
           // hazard 避免
                if ((id_ir[10:8] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))   //无目的寄存器(operand1 = null)
                    reg_A <= ((id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) || (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC)) ? 
                              gr[(id_ir[10:8])] : 
                              ALUo;
					//reg_A <= ALUo;
                else if ((id_ir[10:8] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))  
                    reg_A <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
                else if ((id_ir[10:8] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))  
                    reg_A <= reg_C1;
                else
                    reg_A <= gr[(id_ir[10:8])];   //取出r1 #############
           end
               
          //[------------- LUWEICHENG -------------]
         //↓[type:R]  r1  r2  r3 形 
         else if ((id_ir[15:11] == `LOAD) || (id_ir[15:11] == `STORE) ||
                  (id_ir[15:11] == `ADD) || (id_ir[15:11] == `CMP) || (id_ir[15:11] == `ADDC) || (id_ir[15:11] == `SUB) || (id_ir[15:11] == `SUBC) || 
                  (id_ir[15:11] == `AND) || (id_ir[15:11] == `OR) || (id_ir[15:11] == `XOR) || (id_ir[15:11] == `SLL) || (id_ir[15:11] == `SRL) || (id_ir[15:11] == `SLA) || (id_ir[15:11] == `SRA) ||
                  (id_ir[15:11] == `LWC_ENCRYPT))
           begin
           //[------------- LUWEICHENG -------------]
           // hazard 避免
                if ((id_ir[6:4] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
                    reg_A <= ALUo;
                else if ((id_ir[6:4] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
                    reg_A <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
                else if ((id_ir[6:4] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
                    reg_A <= reg_C1;
                else
           //[------------- LUWEICHENG -------------]
                    reg_A <= gr[(id_ir[6:4])];   //取出r2 #############
           end
         else if (((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1)) ||  
                  ((mem_ir[15:11] == `BNZ) && (zf == 1'b0))|| ((mem_ir[15:11] == `BNN) && (nf == 1'b0))||  
                  ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0))||   
                    mem_ir[15:11] == `JMPR)  
            reg_A <= 16'b0000_0000_0000_0000;  
         else   ; 
        
         /********************* 
            reg_B赋予：第二个操作数***************************************************************************************************************
         ******************** */
         if (id_ir[15:11] == `LOAD)
             reg_B <= {12'b000000000000, id_ir[3:0]};   //r1,r2,val3形：只取val3,需要在前面补12位0 ###########
             
         else if (id_ir[15:11] == `STORE)
           begin
			   reg_B <= {12'b000000000000, id_ir[3:0]};   //r1,r2,val3形：只取val3,需要在前面补12位0 ###########
			   //[------------- LUWEICHENG -------------]
			   //smdr的赋值也需要：hazard 避免
			   if ((id_ir[10:8] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
					smdr <= ALUo;
			   else if ((id_ir[10:8] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
					smdr <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
			   else if ((id_ir[10:8] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
					smdr <= reg_C1;
			   else
			   //[------------- LUWEICHENG -------------]
					smdr  <= gr[id_ir[10:8]];   //STORE #############
           end
		 else if ((id_ir[15:11] == `SLL) || (id_ir[15:11] == `SRL) || (id_ir[15:11] == `SLA) || (id_ir[15:11] == `SRA))
			 reg_B <= {12'b000000000000, id_ir[3:0]};   //r1,r2,val3形：只取val3,需要在前面补12位0 ###########
         else if ((id_ir[15:11] == `ADDI) || (id_ir[15:11] == `SUBI) || 
                  (id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) ||
                  (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC))              
             reg_B <= {8'b00000000, id_ir[7:0]};     // r1 val2 val3, 取出{val2,val3}的组合,需要在前面补8位0 ###########
	     else if ((id_ir[15:11] == `LDIH))   
			 reg_B <= {id_ir[7:0], 8'b00000000};
         else if ((id_ir[15:11] == `ADD) || (id_ir[15:11] == `CMP) || (id_ir[15:11] == `ADDC) || (id_ir[15:11] == `SUB) || (id_ir[15:11] == `SUBC) || 
                  (id_ir[15:11] == `AND) || (id_ir[15:11] == `OR) || (id_ir[15:11] == `XOR) || 
                  (id_ir[15:11] == `LWC_ENCRYPT))   
               begin
               //[------------- LUWEICHENG -------------]
               // hazard 避免
               if ((id_ir[2:0] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
                    reg_B <= ALUo;
               else if ((id_ir[2:0] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
                    reg_B <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
               else if ((id_ir[2:0] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
                    reg_B <= reg_C1;
               else
                    // r1 r2 r3，取出r3； #############
                    reg_B <= gr[id_ir[2:0]];   
               //[------------- LUWEICHENG -------------]
               end
         else if (((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1))||  
			      ((mem_ir[15:11] == `BNZ) && (zf == 1'b0)) || ((mem_ir[15:11] == `BNN) && (nf == 1'b0))||  
			      ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0))||   
				    mem_ir[15:11] == `JMPR)  
            reg_B <= 16'b0000_0000_0000_0000;  
         else   ;
         
       end
end
 
// EX Block (3rd Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         mem_ir <= 16'b0000000000000000;
         reg_C <= 16'b0000000000000000;
         smdr1 <= 16'b0000000000000000;
         zf <= 1'b0 ; 
         nf <= 1'b0 ; 
         dw <= 1'b0 ;
       end
     else if(state==`exec||state==`interrupt)
       begin
         mem_ir <= ex_ir;
         reg_C  <= ALUo;    //reg_C转存ALUo运算结果
		 smdr1 <= smdr;
         
         //flag更新
         if ((ex_ir[15:11] == `ADDI) || (ex_ir[15:11] == `SUBI) || (ex_ir[15:11] == `LDIH) ||
             (ex_ir[15:11] == `ADD) || (ex_ir[15:11] == `CMP) || (ex_ir[15:11] == `ADDC) || (ex_ir[15:11] == `SUB) || (ex_ir[15:11] == `SUBC))  // || (ex_ir[15:11] == `AND) || (ex_ir[15:11] == `OR) || (ex_ir[15:11] == `XOR) || (ex_ir[15:11] == `SLL) || (ex_ir[15:11] == `SRL) || (ex_ir[15:11] == `SLA) || (ex_ir[15:11] == `SRA)
           begin
             if (ALUo == 16'b0000000000000000)
                zf <= 1'b1;
             else
                zf <= 1'b0;
             if (ALUo [15] == 1'b1)
                nf <= 1'b1;
             else
                nf <= 1'b0;
           end
		 else begin
				zf <= zf;
				nf <= nf;
		 end

         if (ex_ir[15:11] == `STORE)
            begin
              dw <= 1'b1;
              //smdr1 <= smdr;
            end
         else
            dw <= 1'b0;
       end
    end
 
// MEM Block (4th Stege)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         wb_ir  <= 16'b0000000000000000;
         reg_C1 <= 16'b0000000000000000;
       end
     else if(state==`exec||state == `interrupt)
       begin	     
         wb_ir  <= mem_ir;
         if (mem_ir[15:11] == `LOAD)
            //**** `LOAD回路：从dmem取得的数据在d_datain中，先给到reg_C1,然后转存到cpu内部存储gr。程序运行其他操作时，时再从gr取数据。
            //其实reg_C一直作为dmem的地址索引，但只有LOAD指令时，cpu才会从dmem中取出数据存入regC_1；其余时候reg_C1转存运算结果reg_C。
            reg_C1 <= d_datain;      
	     else
            reg_C1 <= reg_C;
       end
    end
 
// WB Block (5th Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         gr[0] <= 16'b0000000000000000;
         gr[1] <= 16'b0000000000000000;
         gr[2] <= 16'b0000000000000000;
         gr[3] <= 16'b0000000000000000;
         gr[4] <= 16'b0000000000000000;
         gr[5] <= 16'b0000000000000000;
         gr[6] <= 16'b0000000000000000;
         gr[7] <= 16'b0000000000000000;
       end
     else if(state==`exec||state==`interrupt)
       begin
         if (wb_ir[10:8] != 3'b000)
            if ((wb_ir[15:11] == `LOAD) ||
                (wb_ir[15:11] == `ADDI) || (wb_ir[15:11] == `SUBI) || (wb_ir[15:11] == `LDIH) ||
                (wb_ir[15:11] == `ADD) || (wb_ir[15:11] == `CMP) || (wb_ir[15:11] == `ADDC) || (wb_ir[15:11] == `SUB) || (wb_ir[15:11] == `SUBC) || 
                (wb_ir[15:11] == `AND) || (wb_ir[15:11] == `OR) || (wb_ir[15:11] == `XOR) || (wb_ir[15:11] == `SLL) || (wb_ir[15:11] == `SRL) || (wb_ir[15:11] == `SLA) || (wb_ir[15:11] == `SRA) ||
                (wb_ir[15:11] == `LWC_ENCRYPT))
                    gr[wb_ir[10:8]] <= reg_C1;
			else  
					gr[wb_ir[10:8]] <= gr[wb_ir[10:8]];  
       end
    end

// ALU module
always @(reg_A or reg_B or ex_ir[15:11])
    case (ex_ir[15:11])
     `LOAD   : ALUo <= reg_A + reg_B;
     `STORE  : ALUo <= reg_A + reg_B;
     `ADD    : {cf,ALUo} <= reg_A + reg_B;
     `CMP    : {cf,ALUo} <= reg_A - reg_B;
     `BZ     : ALUo <= reg_A + reg_B;
     `BN     : ALUo <= reg_A + reg_B;
     //[------------- LUWEICHENG -------------]
     // Basic operations
     `ADDC   : {cf,ALUo} <= reg_A + reg_B + cf;
     `SUB    : {cf,ALUo} <= reg_A - reg_B;
     `SUBC   : {cf,ALUo} <= reg_A - reg_B - cf;
     `ADDI   : {cf,ALUo} <= reg_A + reg_B;
     `SUBI   : {cf,ALUo} <= reg_A - reg_B;
     `LDIH   : {cf,ALUo} <= reg_A + reg_B;
     // Logical/Shift operations
     `AND    :  begin   ALUo <= reg_A & reg_B;  cf <= 1'b0;     end
     `OR     :  begin   ALUo <= reg_A | reg_B;  cf <= 1'b0;     end
     `XOR    :  begin   ALUo <= reg_A ^ reg_B;  cf <= 1'b0;     end
     `SLL    :  begin   ALUo <= reg_A << reg_B[3:0];  cf <= 1'b0;     end  
     `SRL    :  begin   ALUo <= reg_A >> reg_B[3:0];  cf <= 1'b0;     end
	 //[注]老版本iverilog编译器不认识>>>和<<<运算符，必须手动实现算数左右移。 2025.2.7
     //`SLA    :  begin  	ALUo <= reg_A <<< reg_B[3:0];  cf <= 1'b0;  end
     //`SRA    :  begin   ALUo <= reg_A >>> reg_B[3:0];  cf <= 1'b0;  end
	 `SLA    :  begin
					if(reg_A[15] == 1'b1)
						ALUo <= 16'h8000 | (reg_A << reg_B[3:0]);  //8000 = 1000_0000_0000_0000 
				    else if(reg_A[15] == 1'b0)
						ALUo <= 16'h7FFF & (reg_A << reg_B[3:0]);  //7FFF = 0111_1111_1111_1111
				    else
						ALUo <= 16'bx;
				end
	 `SRA   :   begin
					if(reg_A[15] == 1'b1)
						ALUo <= ({16{1'b1}} << (16 - reg_B[3:0])) | (reg_A >> reg_B[3:0]);   //({16{1'b1}} << (16 - reg_B[3:0]))生成高位全1的掩码
				    else if(reg_A[15] == 1'b0)
						ALUo <= reg_A >> reg_B[3:0];
					else
						ALUo <= 16'bx;
				end
     `LWC_ENCRYPT:  ALUo <= {reg_A[15:8]^reg_B[7:0], reg_A[7:4]^reg_B[11:8], reg_A[3:0]^reg_B[15:12]};
     
     // Control operations
     `JMPR   :  ALUo <= reg_A + reg_B;
     `BNZ    :  ALUo <= reg_A + reg_B;
     `BNN    :  ALUo <= reg_A + reg_B;
     `BC     :  ALUo <= reg_A + reg_B;
     `BNC    :  ALUo <= reg_A + reg_B;
     //[------------- LUWEICHENG -------------]
     default : begin
            ALUo <= ALUo;
            cf <= cf;
     end
   endcase

// Debug
always @(select_y or gr[1] or gr[2] or gr[3] or gr[4] or gr[5] or gr[6]
         or gr[7] or reg_A or reg_B or reg_C or reg_C1 or smdr or id_ir
         or dw or zf or nf or pc)
   begin
      case (select_y)
       4'b0000 : y = {3'b000, dw, 2'b00, zf, nf, pc};
       4'b0001 : y = gr[1];
       4'b0010 : y = gr[2];
       4'b0011 : y = gr[3];
       4'b0100 : y = gr[4];
       4'b0101 : y = gr[5];
       4'b0110 : y = gr[6];
       4'b0111 : y = gr[7];
       4'b1000 : y = reg_A;
       4'b1001 : y = reg_B;
       4'b1011 : y = reg_C;
       4'b1100 : y = reg_C1;
       4'b1101 : y = smdr;
       4'b1110 : y = id_ir;
       default : y = 16'bXXXXXXXXXXXXXXXX ;
     endcase
   end

endmodule

代码（创新版：可以实现中断和回调）

中断和回调的实现方法在报告中已经详细说明，这里直接粘贴报告中的文字描述和图片进行解释。

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`define NOP   5'b00000
`define HALT  5'b00001
`define LOAD  5'b00010
`define STORE 5'b00011
`define ADD   5'b01000
`define CMP   5'b01100
`define BZ    5'b11010
`define BN    5'b11100
//[------------- LUWEICHENG -------------]
// Basic operations
`define SUB   5'b01010
`define SUBC  5'b10010
`define ADDC  5'b10001
`define ADDI  5'b01001
`define SUBI  5'b01011
`define LDIH  5'b10000
// Logical/Shift operations
`define AND   5'b01101
`define OR    5'b01110
`define XOR   5'b01111
`define SLL   5'b00100
`define SRL   5'b00101
`define SLA   5'b00110
`define SRA   5'b00111
// Control operations
`define JUMP  5'b11000
`define JMPR  5'b11001
`define BNZ   5'b11011
`define BNN   5'b11101
`define BC    5'b11110
`define BNC   5'b11111 
//** LWC original operations
`define LWC_CLEAR       5'b10011   //clear: clear one data in rg[val3] 【CLEAR null null val3】
`define LWC_CA          5'b10100   //CA: celete all data in rg  【no op1op2op3, like NOP & HALT】
`define LWC_ENCRYPT     5'b10101   //encrypt: 数据加密  【LWC_ENCRYPT r1 r2 r3】  秘钥：r3; 源码：r2；加密结果存放在r1，秘钥存放在r1+1.
`define LWC_INTERRUPT   5'b10110   //Interrupt: 中断 (Control operation)  
`define LWC_CALLBACK    5'b10111   //CallBack: 中断回调
//[------------- LUWEICHENG -------------]

// FSM for CPU controler
`define idle 2'b00
`define exec 2'b01
`define interrupt 2'b10


module pcpu (reset, clock, enable, start, i_addr, i_datain, i_datain_interrupt, d_addr,
             d_datain, d_dataout, d_we, select_y, y);

input reset, clock, enable, start;   //由顶层于外部连接，由外部(仿真时)控制
input  [15:0] i_datain;
input  [15:0] i_datain_interrupt;
output [7:0]  i_addr;
output [7:0]  d_addr;
input  [15:0] d_datain;
output [15:0] d_dataout;
output d_we;

// for Debug ------------ 只是用y看一下内部各个线上的数据
input  [3:0] select_y;
output [15:0] y; 

// Definition of F/Fs
reg [7:0]  pc ;                              //pc:  取指令的指针，指向imem内下一条要执行的指令。
reg [15:0] id_ir, ex_ir, mem_ir, wb_ir;      //xx_ir: 指令链，不同阶段对指令instruction进行流水线式的存储。
reg [15:0] gr [0:7];                         //gr: General Register。它是CPU内部的存储器(寄存器堆)。
reg [15:0] reg_A, reg_B, reg_C, reg_C1;      //reg_X: 数据寄存器，用于CPU内部运算数据的暂存。 [reg_A,reg_B] --> ALU --> [reg_C]
reg [15:0] smdr, smdr1;                      //smdr: 直接存储数据
reg zf, nf, dw;       //flags:  zf(zero flag);  nf(negative flag);  dw(data write):与d_we相连，是CPU->dmem写使能。
//[------------- LUWEICHENG -------------]
reg cf;                  //carry flag: 进位信号
reg[7:0] pc_interrupt;   //记录中断前的pc值，中断回调后pc置为 pc_interrupt+1
reg inter_flag;
//[------------- LUWEICHENG -------------]
reg[1:0] state;

// Definition of temporary variables
reg [15:0] ALUo;
reg [15:0] y;
reg[1:0] next_state;

assign i_addr = pc;  //pc给到i_addr，i_addr输出到imem，取出一条指令
assign d_we  = dw;
assign d_addr = reg_C[7:0];   //从dmem中取data的地址，地址始终存在reg_C中
assign d_dataout = smdr1;


// CPU Control (FSM)
always @(posedge clock or negedge reset)
    begin
      if (!reset)
         state <= `idle;
      else
         state <= next_state;
    end

always @(state or enable or start or wb_ir[15:11])
    begin
       case (state)
        `idle : if ((enable == 1'b1) && (start == 1'b1))
                   next_state <= `exec;
                else
                   next_state <= `idle;
        `exec : if ((enable == 1'b0) || (wb_ir[15:11] == `HALT))
                   next_state <= `idle;
                else if ((enable == 1'b0) || (id_ir[15:11] == `LWC_INTERRUPT))
                   next_state <= `interrupt;
                else
                   next_state <= `exec;
         `interrupt: if (id_ir[15:11] == `LWC_CALLBACK)
                        next_state <= `exec;
                     else
                        next_state <= `interrupt;
      endcase
     end
 
// IF Block (1st Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         id_ir <= 16'b0000000000000000;
         pc    <= 8'b00000000;
         pc_interrupt <= 8'b00000000;
         inter_flag <= 0;
       end
     else if(state==`exec||state==`interrupt)
       begin
         // id_ir <= i_datain;     //从imem取指令
         id_ir <= (state == `interrupt) ? i_datain_interrupt : i_datain;
        //主要任务：pc指针控制
         if ( ((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1)) ||
              (mem_ir[15:11] == `JMPR) ||
              ((mem_ir[15:11] == `BNZ) && (zf == 1'b0)) || ((mem_ir[15:11] == `BNN) && (nf == 1'b0)) || ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0)) )      
            //特殊指令跳转： jump to reg_C[7:0]，跳转到ALU运算出来的指令地址。
            pc <= reg_C[7:0];
         else if (id_ir[15:11] == `JUMP)    
            //JUMP指令跳转: jump to {val2,val3}, 中括号的意思是[7:4]与[3:0]组合为[7:0]
            pc <= id_ir[7:0];          
         //[------------- LUWEICHENG -------------] 
         //interrupt & callback
         else if (id_ir[15:11] == `LWC_INTERRUPT)  begin
            pc <= 0;                                         //转到imem_interrupt,从0开始
            if(inter_flag == 0) begin
                pc_interrupt <= pc;                           //记录中断前的pc值
                inter_flag <= 1;
            end
         end
         else if (id_ir[15:11] == `LWC_CALLBACK)  begin
            pc <= pc_interrupt;                                //回到imem
         end
          //[------------- LUWEICHENG -------------]
         else
            pc <= pc + 1;
       end
     else if(state==`idle)   //pc停止
        pc <= pc;
     else ;
    end
 
// ID Block (2nd Stage)
always @(posedge clock or negedge reset)
begin
     if (!reset)
       begin
         ex_ir <= 16'b0000000000000000;
         reg_A <= 16'b0000000000000000;
         reg_B <= 16'b0000000000000000;
         smdr  <= 16'b0000000000000000;
       end
     else if(state==`exec||state==`interrupt)
     begin
         ex_ir <= id_ir;   //ir传递（id -> ex）
         //[------------- LUWEICHENG -------------]
         //The general register clearing operations LWC_CLEAR and LWC_CA are executed 
         //directly in the ID stage, no need to wait until the WB
         if (id_ir[15:11] == `LWC_CA)   begin
            gr[0] = 16'b0000000000000000;   
            gr[1] = 16'b0000000000000000;
            gr[2] = 16'b0000000000000000;
            gr[3] = 16'b0000000000000000;
            gr[4] = 16'b0000000000000000;
            gr[5] = 16'b0000000000000000;
            gr[6] = 16'b0000000000000000;
            gr[7] = 16'b0000000000000000;           
         end
         else if (id_ir[15:11] == `LWC_CLEAR) begin  //clear: clear one data in rg[val3] 【CLEAR null null val3】
            gr[id_ir[3:0]] = 16'b0000000000000000;
         end
         else   ;
         //[------------- LUWEICHENG -------------]
         /******************** 
            reg_A 赋予：第一个操作数  ***************************************************************************************************************
         *********************/
         //↓[type:I]  r1  val2  val3 形 
         if ((id_ir[15:11] == `ADDI) || (id_ir[15:11] == `SUBI) || (id_ir[15:11] == `LDIH) ||
             (id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) ||
             (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC)) 
           begin
           //[------------- LUWEICHENG -------------]
           // hazard 避免
                if ((id_ir[10:8] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))   //无目的寄存器(operand1 = null)
                    reg_A <= ((id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) || (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC)) ? 
                              gr[(id_ir[10:8])]: 
                              ALUo;
                else if ((id_ir[10:8] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))  
                    reg_A <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
                else if ((id_ir[10:8] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))  
                    reg_A <= reg_C1;
                else
                    reg_A <= gr[(id_ir[10:8])];   //取出r1 #############
           end
               
          //[------------- LUWEICHENG -------------]
         //↓[type:R]  r1  r2  r3 形 
         else if ((id_ir[15:11] == `LOAD) || (id_ir[15:11] == `STORE) ||
                  (id_ir[15:11] == `ADD) || (id_ir[15:11] == `CMP) || (id_ir[15:11] == `ADDC) || (id_ir[15:11] == `SUB) || (id_ir[15:11] == `SUBC) || 
                  (id_ir[15:11] == `AND) || (id_ir[15:11] == `OR) || (id_ir[15:11] == `XOR) || (id_ir[15:11] == `SLL) || (id_ir[15:11] == `SRL) || (id_ir[15:11] == `SLA) || (id_ir[15:11] == `SRA) ||
                  (id_ir[15:11] == `LWC_ENCRYPT))
           begin
           //[------------- LUWEICHENG -------------]
           // hazard 避免
                if ((id_ir[6:4] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
                    reg_A <= ALUo;
                else if ((id_ir[6:4] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
                    reg_A <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
                else if ((id_ir[6:4] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
                    reg_A <= reg_C1;
                else
           //[------------- LUWEICHENG -------------]
                    reg_A <= gr[(id_ir[6:4])];   //取出r2 #############
           end
         else if (((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1)) ||  
                  ((mem_ir[15:11] == `BNZ) && (zf == 1'b0))|| ((mem_ir[15:11] == `BNN) && (nf == 1'b0))||  
                  ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0))||   
                    mem_ir[15:11] == `JMPR)  
            reg_A <= 16'b0000_0000_0000_0000;  
         else   ; 
        
         /********************* 
            reg_B赋予：第二个操作数***************************************************************************************************************
         ******************** */
         if (id_ir[15:11] == `LOAD)
             reg_B <= {12'b000000000000, id_ir[3:0]};   //val3 #############
             
         else if (id_ir[15:11] == `STORE)
           begin
             reg_B <= {12'b000000000000, id_ir[3:0]};  
           //[------------- LUWEICHENG -------------]
           //smdr的赋值也需要：hazard 避免
           if ((id_ir[10:8] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
                smdr <= ALUo;
           else if ((id_ir[10:8] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
                smdr <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
           else if ((id_ir[10:8] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
                smdr <= reg_C1;
           else
           //[------------- LUWEICHENG -------------]
                smdr  <= gr[id_ir[10:8]];   //STORE #############
           end
         else if ((id_ir[15:11] == `SLL) || (id_ir[15:11] == `SRL) || (id_ir[15:11] == `SLA) || (id_ir[15:11] == `SRA))
			 reg_B <= {12'b000000000000, id_ir[3:0]};   //r1,r2,val3形：只取val3,需要在前面补12位0 ###########  
         else if ((id_ir[15:11] == `ADDI) || (id_ir[15:11] == `SUBI) ||
                  (id_ir[15:11] == `BZ) || (id_ir[15:11] == `BN) ||
                  (id_ir[15:11] == `JMPR) || (id_ir[15:11] == `BNZ) || (id_ir[15:11] == `BNN) || (id_ir[15:11] == `BC) || (id_ir[15:11] == `BNC))   
             reg_B <= {8'b00000000, id_ir[7:0]};   // r1 val2 val3, 取出{val2,val3}的组合,需要在前面补8位0 ###########
         else if (id_ir[15:11] == `LDIH)
             reg_B <= {id_ir[7:0], 8'b00000000};   //LDIH较为特殊，取出{val2,val3}的组合后，在后面补8个0 ###########
         else if ((id_ir[15:11] == `ADD) || (id_ir[15:11] == `CMP) || (id_ir[15:11] == `ADDC) || (id_ir[15:11] == `SUB) || (id_ir[15:11] == `SUBC) || 
                  (id_ir[15:11] == `AND) || (id_ir[15:11] == `OR) || (id_ir[15:11] == `XOR) || 
                  (id_ir[15:11] == `LWC_ENCRYPT))   
               begin
               //[------------- LUWEICHENG -------------]
               // hazard 避免
               if ((id_ir[2:0] == ex_ir[10:8]) && (ex_ir[15:11]!=`NOP) && (ex_ir[15:11]!=`CMP) && (ex_ir[15:11]!=`JUMP) && (ex_ir[15:11]!=`LOAD) && (ex_ir[15:11]!=`HALT))
                    reg_B <= ALUo;
               else if ((id_ir[2:0] == mem_ir[10:8]) && (mem_ir[15:11]!=`NOP) && (mem_ir[15:11]!=`CMP) && (mem_ir[15:11]!=`JUMP) && (mem_ir[15:11]!=`HALT))
                    reg_B <= (mem_ir[15:11] == `LOAD) ? d_datain : reg_C;
               else if ((id_ir[2:0] == wb_ir[10:8]) && (wb_ir[15:11]!=`NOP) && (wb_ir[15:11]!=`CMP) && (wb_ir[15:11]!=`JUMP) && (wb_ir[15:11]!=`HALT))
                    reg_B <= reg_C1;
               else
                    // r1 r2 r3，取出r3； #############
                    reg_B <= gr[id_ir[2:0]];   
               //[------------- LUWEICHENG -------------]
               end
         else if (((mem_ir[15:11] == `BZ) && (zf == 1'b1)) || ((mem_ir[15:11] == `BN) && (nf == 1'b1))||  
			      ((mem_ir[15:11] == `BNZ) && (zf == 1'b0)) || ((mem_ir[15:11] == `BNN) && (nf == 1'b0))||  
			      ((mem_ir[15:11] == `BC) && (cf == 1'b1)) || ((mem_ir[15:11] == `BNC) && (cf == 1'b0))||   
				    mem_ir[15:11] == `JMPR)  
            reg_B <= 16'b0000_0000_0000_0000;  
         else   ;
         
       end
end
 
// EX Block (3rd Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         mem_ir <= 16'b0000000000000000;
         reg_C <= 16'b0000000000000000;
         smdr1 <= 16'b0000000000000000;
         zf <= 1'b0 ; 
         nf <= 1'b0 ; 
         dw <= 1'b0 ;
       end
     else if(state==`exec||state==`interrupt)
       begin
         mem_ir <= ex_ir;
         reg_C  <= ALUo;    //reg_C转存ALUo运算结果
         smdr1 <= smdr;
         //flag更新
         if ((ex_ir[15:11] == `ADDI) || (ex_ir[15:11] == `SUBI) || (ex_ir[15:11] == `LDIH) ||
             (ex_ir[15:11] == `ADD) || (ex_ir[15:11] == `CMP) || (ex_ir[15:11] == `ADDC) || (ex_ir[15:11] == `SUB) || (ex_ir[15:11] == `SUBC) || 
             (ex_ir[15:11] == `AND) || (ex_ir[15:11] == `OR) || (ex_ir[15:11] == `XOR) || (ex_ir[15:11] == `SLL) || (ex_ir[15:11] == `SRL) || (ex_ir[15:11] == `SLA) || (ex_ir[15:11] == `SRA))
           begin
             if (ALUo == 16'b0000000000000000)
                zf <= 1'b1;
             else
                zf <= 1'b0;
             if (ALUo [15] == 1'b1)
                nf <= 1'b1;
             else
                nf <= 1'b0;
           end

         if (ex_ir[15:11] == `STORE)
            begin
              dw <= 1'b1;
              //smdr1 <= smdr;
            end
         else
            dw <= 1'b0;
       end
    end
 
// MEM Block (4th Stege)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         wb_ir  <= 16'b0000000000000000;
         reg_C1 <= 16'b0000000000000000;
       end
     else if(state==`exec||state == `interrupt)
       begin
         wb_ir  <= mem_ir;
         if (mem_ir[15:11] == `LOAD)
            //**** `LOAD回路：从dmem取得的数据在d_datain中，先给到reg_C1,然后转存到cpu内部存储gr。程序运行其他操作时，时再从gr取数据。
            //其实reg_C一直作为dmem的地址索引，但只有LOAD指令时，cpu才会从dmem中取出数据存入regC_1；其余时候reg_C1转存运算结果reg_C。
            reg_C1 <= d_datain;      
	     else
            reg_C1 <= reg_C;
       end
    end
 
// WB Block (5th Stage)
always @(posedge clock or negedge reset)
    begin
     if (!reset)
       begin
         gr[0] <= 16'b0000000000000000;
         gr[1] <= 16'b0000000000000000;
         gr[2] <= 16'b0000000000000000;
         gr[3] <= 16'b0000000000000000;
         gr[4] <= 16'b0000000000000000;
         gr[5] <= 16'b0000000000000000;
         gr[6] <= 16'b0000000000000000;
         gr[7] <= 16'b0000000000000000;
       end
     else if(state==`exec||state==`interrupt)
       begin
         if (wb_ir[10:8] != 3'b000)
            if ((wb_ir[15:11] == `LOAD) ||
                (wb_ir[15:11] == `ADDI) || (wb_ir[15:11] == `SUBI) || (wb_ir[15:11] == `LDIH) ||
                (wb_ir[15:11] == `ADD) || (wb_ir[15:11] == `CMP) || (wb_ir[15:11] == `ADDC) || (wb_ir[15:11] == `SUB) || (wb_ir[15:11] == `SUBC) || 
                (wb_ir[15:11] == `AND) || (wb_ir[15:11] == `OR) || (wb_ir[15:11] == `XOR) || (wb_ir[15:11] == `SLL) || (wb_ir[15:11] == `SRL) || (wb_ir[15:11] == `SLA) || (wb_ir[15:11] == `SRA) ||
                (wb_ir[15:11] == `LWC_ENCRYPT))
                    gr[wb_ir[10:8]] <= reg_C1;
            else  
					gr[wb_ir[10:8]] <= gr[wb_ir[10:8]];  
       end
    end

// ALU module
always @(reg_A or reg_B or ex_ir[15:11])
    case (ex_ir[15:11])
     `LOAD   : ALUo <= reg_A + reg_B;
     `STORE  : ALUo <= reg_A + reg_B;
     `ADD    : {cf,ALUo} <= reg_A + reg_B;
     `CMP    : {cf,ALUo} <= reg_A - reg_B;
     `BZ     : ALUo <= reg_A + reg_B;
     `BN     : ALUo <= reg_A + reg_B;
     //[------------- LUWEICHENG -------------]
     // Basic operations
     `ADDC   : {cf,ALUo} <= reg_A + reg_B + cf;
     `SUB    : {cf,ALUo} <= reg_A - reg_B;
     `SUBC   : {cf,ALUo} <= reg_A - reg_B - cf;
     `ADDI   : {cf,ALUo} <= reg_A + reg_B;
     `SUBI   : {cf,ALUo} <= reg_A - reg_B;
     `LDIH   : {cf,ALUo} <= reg_A + reg_B;
     // Logical/Shift operations
     `AND    :  begin   ALUo <= reg_A & reg_B;  cf <= 1'b0;     end
     `OR     :  begin   ALUo <= reg_A | reg_B;  cf <= 1'b0;     end
     `XOR    :  begin   ALUo <= reg_A ^ reg_B;  cf <= 1'b0;     end
     `SLL    :  begin   ALUo <= reg_A << reg_B[3:0];  cf <= 1'b0;     end  //reg_B[3:0]存放的是val3，也就是ir[3:0]
     `SRL    :  begin   ALUo <= reg_A >> reg_B[3:0];  cf <= 1'b0;     end
     `SLA    :  begin
					if(reg_A[15] == 1'b1)
						ALUo <= 16'h8000 | (reg_A << reg_B[3:0]);  //8000 = 1000_0000_0000_0000 
				    else if(reg_A[15] == 1'b0)
						ALUo <= 16'h7FFF & (reg_A << reg_B[3:0]);  //7FFF = 0111_1111_1111_1111
				    else
						ALUo <= 16'bx;
				end
	 `SRA   :   begin
					if(reg_A[15] == 1'b1)
						ALUo <= ({16{1'b1}} << (16 - reg_B[3:0])) | (reg_A >> reg_B[3:0]);   //({16{1'b1}} << (16 - reg_B[3:0]))生成高位全1的掩码
				    else if(reg_A[15] == 1'b0)
						ALUo <= reg_A >> reg_B[3:0];
					else
						ALUo <= 16'bx;
				end
     `LWC_ENCRYPT:  ALUo <= {reg_A[15:8]^reg_B[7:0], reg_A[7:4]^reg_B[11:8], reg_A[3:0]^reg_B[15:12]};
     
     // Control operations
     `JMPR   :  ALUo <= reg_A + reg_B;
     `BNZ    :  ALUo <= reg_A + reg_B;
     `BNN    :  ALUo <= reg_A + reg_B;
     `BC     :  ALUo <= reg_A + reg_B;
     `BNC    :  ALUo <= reg_A + reg_B;
     //[------------- LUWEICHENG -------------]
     default : begin
            ALUo <= ALUo;
            cf <= cf;
     end
   endcase

// Debug
always @(select_y or gr[1] or gr[2] or gr[3] or gr[4] or gr[5] or gr[6]
         or gr[7] or reg_A or reg_B or reg_C or reg_C1 or smdr or id_ir
         or dw or zf or nf or pc)
   begin
      case (select_y)
       4'b0000 : y = {3'b000, dw, 2'b00, zf, nf, pc};
       4'b0001 : y = gr[1];
       4'b0010 : y = gr[2];
       4'b0011 : y = gr[3];
       4'b0100 : y = gr[4];
       4'b0101 : y = gr[5];
       4'b0110 : y = gr[6];
       4'b0111 : y = gr[7];
       4'b1000 : y = reg_A;
       4'b1001 : y = reg_B;
       4'b1011 : y = reg_C;
       4'b1100 : y = reg_C1;
       4'b1101 : y = smdr;
       4'b1110 : y = id_ir;
       default : y = 16'bXXXXXXXXXXXXXXXX ;
     endcase
   end

endmodule
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